Tiny NoC: A 3D mesh topology with router channel optimization for area and latency minimization

Cesar Marcon; Ramon Fernandes; Rodrigo Cataldo; Fernando Grando; Thais Webber; Ana Benso; Leticia B. Poehls

doi:10.1109/VLSID.2014.46

Tiny NoC: A 3D mesh topology with router channel optimization for area and latency minimization

Cesar Marcon, Ramon Fernandes, Rodrigo Cataldo, Fernando Grando, Thais Webber, Ana Benso, Leticia B. Poehls

School of Computer Science

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

13 Citations (Scopus)

Abstract

This paper presents Tiny NoC, which is a scalable and efficient 3D mesh architecture developed to minimize latency and NoC area. First, we show a theoretical analysis of latency and area occupancy to demonstrate Tiny NoC efficiency when compared to a basic mesh NoC. Then, we select a set of synthetic and mapping independent traffic with several injection rates to analyze the advantages and weaknesses of Tiny NoC. The experimental results highlight that Tiny NoC always reduces area occupancy and for several cases it provides latency minimization.

Original language	English
Title of host publication	Proceedings - 27th International Conference on VLSI Design, VLSID 2014; Held Concurrently with 13th International Conference on Embedded Systems Design
Pages	228-233
Number of pages	6
DOIs	https://doi.org/10.1109/VLSID.2014.46
Publication status	Published - 2014
Event	27th International Conference on VLSI Design, VLSID 2014 - Held Concurrently with 13th International Conference on Embedded Systems Design - Mumbai, India Duration: 5 Jan 2014 → 9 Jan 2014

Publication series

Name	Proceedings of the IEEE International Conference on VLSI Design
ISSN (Print)	1063-9667

Conference

Conference	27th International Conference on VLSI Design, VLSID 2014 - Held Concurrently with 13th International Conference on Embedded Systems Design
Country/Territory	India
City	Mumbai
Period	5/01/14 → 9/01/14

Keywords

3D mesh NoC
Area
Latency
Optimization

Access to Document

10.1109/VLSID.2014.46

Cite this

Marcon, C., Fernandes, R., Cataldo, R., Grando, F., Webber, T., Benso, A., & Poehls, L. B. (2014). Tiny NoC: A 3D mesh topology with router channel optimization for area and latency minimization. In Proceedings - 27th International Conference on VLSI Design, VLSID 2014; Held Concurrently with 13th International Conference on Embedded Systems Design (pp. 228-233). Article 6733135 (Proceedings of the IEEE International Conference on VLSI Design). https://doi.org/10.1109/VLSID.2014.46

Marcon, Cesar ; Fernandes, Ramon ; Cataldo, Rodrigo et al. / Tiny NoC : A 3D mesh topology with router channel optimization for area and latency minimization. Proceedings - 27th International Conference on VLSI Design, VLSID 2014; Held Concurrently with 13th International Conference on Embedded Systems Design. 2014. pp. 228-233 (Proceedings of the IEEE International Conference on VLSI Design).

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title = "Tiny NoC: A 3D mesh topology with router channel optimization for area and latency minimization",

abstract = "This paper presents Tiny NoC, which is a scalable and efficient 3D mesh architecture developed to minimize latency and NoC area. First, we show a theoretical analysis of latency and area occupancy to demonstrate Tiny NoC efficiency when compared to a basic mesh NoC. Then, we select a set of synthetic and mapping independent traffic with several injection rates to analyze the advantages and weaknesses of Tiny NoC. The experimental results highlight that Tiny NoC always reduces area occupancy and for several cases it provides latency minimization.",

keywords = "3D mesh NoC, Area, Latency, Optimization",

author = "Cesar Marcon and Ramon Fernandes and Rodrigo Cataldo and Fernando Grando and Thais Webber and Ana Benso and Poehls, {Leticia B.}",

note = "Copyright: Copyright 2014 Elsevier B.V., All rights reserved.; 27th International Conference on VLSI Design, VLSID 2014 - Held Concurrently with 13th International Conference on Embedded Systems Design ; Conference date: 05-01-2014 Through 09-01-2014",

year = "2014",

doi = "10.1109/VLSID.2014.46",

language = "English",

isbn = "9781479925124",

series = "Proceedings of the IEEE International Conference on VLSI Design",

pages = "228--233",

booktitle = "Proceedings - 27th International Conference on VLSI Design, VLSID 2014; Held Concurrently with 13th International Conference on Embedded Systems Design",

}

Marcon, C, Fernandes, R, Cataldo, R, Grando, F, Webber, T, Benso, A & Poehls, LB 2014, Tiny NoC: A 3D mesh topology with router channel optimization for area and latency minimization. in Proceedings - 27th International Conference on VLSI Design, VLSID 2014; Held Concurrently with 13th International Conference on Embedded Systems Design., 6733135, Proceedings of the IEEE International Conference on VLSI Design, pp. 228-233, 27th International Conference on VLSI Design, VLSID 2014 - Held Concurrently with 13th International Conference on Embedded Systems Design, Mumbai, India, 5/01/14. https://doi.org/10.1109/VLSID.2014.46

Tiny NoC: A 3D mesh topology with router channel optimization for area and latency minimization. / Marcon, Cesar; Fernandes, Ramon; Cataldo, Rodrigo et al.
Proceedings - 27th International Conference on VLSI Design, VLSID 2014; Held Concurrently with 13th International Conference on Embedded Systems Design. 2014. p. 228-233 6733135 (Proceedings of the IEEE International Conference on VLSI Design).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - Tiny NoC

T2 - 27th International Conference on VLSI Design, VLSID 2014 - Held Concurrently with 13th International Conference on Embedded Systems Design

AU - Marcon, Cesar

AU - Fernandes, Ramon

AU - Cataldo, Rodrigo

AU - Grando, Fernando

AU - Webber, Thais

AU - Benso, Ana

AU - Poehls, Leticia B.

PY - 2014

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AB - This paper presents Tiny NoC, which is a scalable and efficient 3D mesh architecture developed to minimize latency and NoC area. First, we show a theoretical analysis of latency and area occupancy to demonstrate Tiny NoC efficiency when compared to a basic mesh NoC. Then, we select a set of synthetic and mapping independent traffic with several injection rates to analyze the advantages and weaknesses of Tiny NoC. The experimental results highlight that Tiny NoC always reduces area occupancy and for several cases it provides latency minimization.

KW - 3D mesh NoC

KW - Area

KW - Latency

KW - Optimization

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DO - 10.1109/VLSID.2014.46

M3 - Conference contribution

AN - SCOPUS:84894534830

SN - 9781479925124

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BT - Proceedings - 27th International Conference on VLSI Design, VLSID 2014; Held Concurrently with 13th International Conference on Embedded Systems Design

Y2 - 5 January 2014 through 9 January 2014

ER -

Marcon C, Fernandes R, Cataldo R, Grando F, Webber T, Benso A et al. Tiny NoC: A 3D mesh topology with router channel optimization for area and latency minimization. In Proceedings - 27th International Conference on VLSI Design, VLSID 2014; Held Concurrently with 13th International Conference on Embedded Systems Design. 2014. p. 228-233. 6733135. (Proceedings of the IEEE International Conference on VLSI Design). doi: 10.1109/VLSID.2014.46

Tiny NoC: A 3D mesh topology with router channel optimization for area and latency minimization

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