Test structures for the characterization of MEMS and CMOS integration technology

Huamao Lin; Anthony J. Walton; Camelia C. Dunare; J. Tom M. Stevenson; Alan M. Gundlach; Stewart Smith; Andrew S. Bunting

doi:10.1109/TSM.2008.2000274

Test structures for the characterization of MEMS and CMOS integration technology

Huamao Lin^*, Anthony J. Walton, Camelia C. Dunare, J. Tom M. Stevenson, Alan M. Gundlach, Stewart Smith, Andrew S. Bunting

^*Corresponding author for this work

School of Physics and Astronomy

Research output: Contribution to journal › Article › peer-review

Abstract

Test structures have been used to study the feasibility of bonding MEMS to CMOS wafers to create an integrated system. This involves bonding of prefabricated wafers and creating interconnects between the bonded wafers. Bonding of prefabricated wafers has been demonstrated using a chemical-mechanical polishing enabled surface planarization process and an oxygen plasma assisted low temperature wafer bonding process. Two interwafer connection approaches have been evaluated. For an oxide bonding approach, interconnects between wafers are established through contact vias, using a standard multilevel metallization process after the wafer bonding process. Resistances of 3.8-5.2 Ω have been obtained from via chain test structures and an average specific contact resistivity of 1.7 × 10^-8 Ωcm², measured from the single via Kelvin structures. For a direct metal contact approach, electrical connections have been achieved during the bonding anneal stage due to stress relief of the aluminium film.

Original language	English
Article number	4512055
Pages (from-to)	140-147
Number of pages	8
Journal	IEEE Transactions on Semiconductor Manufacturing
Volume	21
Issue number	2
DOIs	https://doi.org/10.1109/TSM.2008.2000274
Publication status	Published - 1 May 2008

Keywords

Chemical-mechanical polishing (CMP)
Complementary metal-oxide semiconductor (CMOS)-microelectromechanical systems (MEMS) integration
IC interconnections
Kelvin test structure
Low-temperature wafer direct bonding
Plasma activation

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10.1109/TSM.2008.2000274

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title = "Test structures for the characterization of MEMS and CMOS integration technology",

abstract = "Test structures have been used to study the feasibility of bonding MEMS to CMOS wafers to create an integrated system. This involves bonding of prefabricated wafers and creating interconnects between the bonded wafers. Bonding of prefabricated wafers has been demonstrated using a chemical-mechanical polishing enabled surface planarization process and an oxygen plasma assisted low temperature wafer bonding process. Two interwafer connection approaches have been evaluated. For an oxide bonding approach, interconnects between wafers are established through contact vias, using a standard multilevel metallization process after the wafer bonding process. Resistances of 3.8-5.2 Ω have been obtained from via chain test structures and an average specific contact resistivity of 1.7 × 10-8 Ωcm2, measured from the single via Kelvin structures. For a direct metal contact approach, electrical connections have been achieved during the bonding anneal stage due to stress relief of the aluminium film.",

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author = "Huamao Lin and Walton, {Anthony J.} and Dunare, {Camelia C.} and Stevenson, {J. Tom M.} and Gundlach, {Alan M.} and Stewart Smith and Bunting, {Andrew S.}",

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AU - Walton, Anthony J.

AU - Dunare, Camelia C.

AU - Stevenson, J. Tom M.

AU - Gundlach, Alan M.

AU - Smith, Stewart

AU - Bunting, Andrew S.

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N2 - Test structures have been used to study the feasibility of bonding MEMS to CMOS wafers to create an integrated system. This involves bonding of prefabricated wafers and creating interconnects between the bonded wafers. Bonding of prefabricated wafers has been demonstrated using a chemical-mechanical polishing enabled surface planarization process and an oxygen plasma assisted low temperature wafer bonding process. Two interwafer connection approaches have been evaluated. For an oxide bonding approach, interconnects between wafers are established through contact vias, using a standard multilevel metallization process after the wafer bonding process. Resistances of 3.8-5.2 Ω have been obtained from via chain test structures and an average specific contact resistivity of 1.7 × 10-8 Ωcm2, measured from the single via Kelvin structures. For a direct metal contact approach, electrical connections have been achieved during the bonding anneal stage due to stress relief of the aluminium film.

AB - Test structures have been used to study the feasibility of bonding MEMS to CMOS wafers to create an integrated system. This involves bonding of prefabricated wafers and creating interconnects between the bonded wafers. Bonding of prefabricated wafers has been demonstrated using a chemical-mechanical polishing enabled surface planarization process and an oxygen plasma assisted low temperature wafer bonding process. Two interwafer connection approaches have been evaluated. For an oxide bonding approach, interconnects between wafers are established through contact vias, using a standard multilevel metallization process after the wafer bonding process. Resistances of 3.8-5.2 Ω have been obtained from via chain test structures and an average specific contact resistivity of 1.7 × 10-8 Ωcm2, measured from the single via Kelvin structures. For a direct metal contact approach, electrical connections have been achieved during the bonding anneal stage due to stress relief of the aluminium film.

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KW - Plasma activation

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Test structures for the characterization of MEMS and CMOS integration technology

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Keywords

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