Test structures for the characterization of MEMS and CMOS integration technology

Huamao Lin*, Anthony J. Walton, Camelia C. Dunare, J. Tom M. Stevenson, Alan M. Gundlach, Stewart Smith, Andrew S. Bunting

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

5 Citations (Scopus)


Test structures have been used to study the feasibility of bonding MEMS to CMOS wafers to create an integrated system. This involves bonding of prefabricated wafers and creating interconnects between the bonded wafers. Bonding of prefabricated wafers has been demonstrated using a chemical-mechanical polishing enabled surface planarization process and an oxygen plasma assisted low temperature wafer bonding process. Two interwafer connection approaches have been evaluated. For an oxide bonding approach, interconnects between wafers are established through contact vias, using a standard multilevel metallization process after the wafer bonding process. Resistances of 3.8-5.2 Ω have been obtained from via chain test structures and an average specific contact resistivity of 1.7 × 10-8 Ωcm2, measured from the single via Kelvin structures. For a direct metal contact approach, electrical connections have been achieved during the bonding anneal stage due to stress relief of the aluminium film.

Original languageEnglish
Article number4512055
Pages (from-to)140-147
Number of pages8
JournalIEEE Transactions on Semiconductor Manufacturing
Issue number2
Publication statusPublished - 1 May 2008


  • Chemical-mechanical polishing (CMP)
  • Complementary metal-oxide semiconductor (CMOS)-microelectromechanical systems (MEMS) integration
  • IC interconnections
  • Kelvin test structure
  • Low-temperature wafer direct bonding
  • Plasma activation


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