Test structures for the characterisation of MEMS and CMOS integration technology

H. Lin*, A. J. Walton, C. C. Dunare, J. T.M. Stevenson, A. M. Gundlach, S. Smith, A. S. Bunting

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Abstract

Test structures have been used to demonstrate the feasibility of bonding MEMS and CMOS wafers to create an integrated system. This involves using low temperature bonding along with CMP planarisation and wafer thinning. The last step in the integration process is bringing the electrical connections to the top surface and the creation of interconnect between the wafers. Test structures to evaluate this process have been designed and fabricated resulting in 7 - 9 Ω resistances for via chain structures. Via contact resistances of 6 × 10 -8Ω.cm 2 were measured using Kelvin test structures.

Original languageEnglish
Title of host publication2006 International Conference on Microelectronic Test Structures - Digest of Technical Papers
Pages143-148
Number of pages6
Volume2006
DOIs
Publication statusPublished - 13 Oct 2006
Event2006 International Conference on Microelectronic Test Structures - Austin, TX, United States
Duration: 6 Mar 20069 Mar 2006

Conference

Conference2006 International Conference on Microelectronic Test Structures
Country/TerritoryUnited States
CityAustin, TX
Period6/03/069/03/06

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