Test structures for the characterisation of MEMS and CMOS integration technology

H. Lin; A. J. Walton; C. C. Dunare; J. T.M. Stevenson; A. M. Gundlach; S. Smith; A. S. Bunting

doi:10.1109/ICMTS.2006.1614292

Test structures for the characterisation of MEMS and CMOS integration technology

H. Lin^*, A. J. Walton, C. C. Dunare, J. T.M. Stevenson, A. M. Gundlach, S. Smith, A. S. Bunting

^*Corresponding author for this work

School of Physics and Astronomy

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

Test structures have been used to demonstrate the feasibility of bonding MEMS and CMOS wafers to create an integrated system. This involves using low temperature bonding along with CMP planarisation and wafer thinning. The last step in the integration process is bringing the electrical connections to the top surface and the creation of interconnect between the wafers. Test structures to evaluate this process have been designed and fabricated resulting in 7 - 9 Ω resistances for via chain structures. Via contact resistances of 6 × 10 ^-8Ω.cm ² were measured using Kelvin test structures.

Original language	English
Title of host publication	2006 International Conference on Microelectronic Test Structures - Digest of Technical Papers
Pages	143-148
Number of pages	6
Volume	2006
DOIs	https://doi.org/10.1109/ICMTS.2006.1614292
Publication status	Published - 13 Oct 2006
Event	2006 International Conference on Microelectronic Test Structures - Austin, TX, United States Duration: 6 Mar 2006 → 9 Mar 2006

Conference

Conference	2006 International Conference on Microelectronic Test Structures
Country/Territory	United States
City	Austin, TX
Period	6/03/06 → 9/03/06

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10.1109/ICMTS.2006.1614292

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Lin, H., Walton, A. J., Dunare, C. C., Stevenson, J. T. M., Gundlach, A. M., Smith, S., & Bunting, A. S. (2006). Test structures for the characterisation of MEMS and CMOS integration technology. In 2006 International Conference on Microelectronic Test Structures - Digest of Technical Papers (Vol. 2006, pp. 143-148). Article 1614292 https://doi.org/10.1109/ICMTS.2006.1614292

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abstract = "Test structures have been used to demonstrate the feasibility of bonding MEMS and CMOS wafers to create an integrated system. This involves using low temperature bonding along with CMP planarisation and wafer thinning. The last step in the integration process is bringing the electrical connections to the top surface and the creation of interconnect between the wafers. Test structures to evaluate this process have been designed and fabricated resulting in 7 - 9 Ω resistances for via chain structures. Via contact resistances of 6 × 10 -8Ω.cm 2 were measured using Kelvin test structures.",

author = "H. Lin and Walton, {A. J.} and Dunare, {C. C.} and Stevenson, {J. T.M.} and Gundlach, {A. M.} and S. Smith and Bunting, {A. S.}",

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doi = "10.1109/ICMTS.2006.1614292",

language = "English",

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Lin, H, Walton, AJ, Dunare, CC, Stevenson, JTM, Gundlach, AM, Smith, S & Bunting, AS 2006, Test structures for the characterisation of MEMS and CMOS integration technology. in 2006 International Conference on Microelectronic Test Structures - Digest of Technical Papers. vol. 2006, 1614292, pp. 143-148, 2006 International Conference on Microelectronic Test Structures, Austin, TX, United States, 6/03/06. https://doi.org/10.1109/ICMTS.2006.1614292

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AU - Walton, A. J.

AU - Dunare, C. C.

AU - Stevenson, J. T.M.

AU - Gundlach, A. M.

AU - Smith, S.

AU - Bunting, A. S.

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AB - Test structures have been used to demonstrate the feasibility of bonding MEMS and CMOS wafers to create an integrated system. This involves using low temperature bonding along with CMP planarisation and wafer thinning. The last step in the integration process is bringing the electrical connections to the top surface and the creation of interconnect between the wafers. Test structures to evaluate this process have been designed and fabricated resulting in 7 - 9 Ω resistances for via chain structures. Via contact resistances of 6 × 10 -8Ω.cm 2 were measured using Kelvin test structures.

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BT - 2006 International Conference on Microelectronic Test Structures - Digest of Technical Papers

T2 - 2006 International Conference on Microelectronic Test Structures

Y2 - 6 March 2006 through 9 March 2006

ER -

Test structures for the characterisation of MEMS and CMOS integration technology

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