Task partitioning optimization algorithm for energy saving and load balance on NoC-based MPSoCs

Marco P. Stefani; Thais Webber; Ramon Fernandes; Rodrigo Cataldo; Letícia B. Poehls; César Marcon

doi:10.1109/ISQED.2015.7085412

Task partitioning optimization algorithm for energy saving and load balance on NoC-based MPSoCs

Marco P. Stefani, Thais Webber, Ramon Fernandes, Rodrigo Cataldo, Letícia B. Poehls, César Marcon

School of Computer Science

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

Multiprocessor System-on-Chip (MPSoC) based on Network-on-Chip (NoC) integrates a large amount of Processor Elements (PEs) to fulfill the performance requirements of several applications. These applications are composed of a set of intercommunicating tasks, which are dynamically mapped onto PEs of the target architecture. However, the efficient task-mapping requires some previous steps, among them partitioning, which organizes tasks considering their interaction before applying a mapping process. This paper introduces Partition Reduce (PR) - a task partitioning approach based on the MapReduce algorithm targeting homogeneous NoC based MPSoCs. We analyze the efficiency of PR for energy consumption (EC) minimization and load balance (LB). The results obtained from a set of experiments, with large number of tasks, demonstrate that PR is more effective on processing time and result quality when compared to the classic Simulated Annealing (SA). In addition, PR produces partitions with low energy consumption and rigorous load balance.

Original language	English
Title of host publication	Proceedings of the 16th International Symposium on Quality Electronic Design, ISQED 2015
Publisher	IEEE Computer Society
Pages	130-134
Number of pages	5
ISBN (Electronic)	9781479975815
DOIs	https://doi.org/10.1109/ISQED.2015.7085412
Publication status	Published - 13 Apr 2015
Event	16th International Symposium on Quality Electronic Design, ISQED 2015 - Santa Clara, United States Duration: 2 Mar 2015 → 4 Mar 2015

Publication series

Name	Proceedings - International Symposium on Quality Electronic Design, ISQED
Volume	2015-April
ISSN (Print)	1948-3287
ISSN (Electronic)	1948-3295

Conference

Conference	16th International Symposium on Quality Electronic Design, ISQED 2015
Country/Territory	United States
City	Santa Clara
Period	2/03/15 → 4/03/15

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

Keywords

energy efficiency
homogeneous MPSoC
load balance
NoC
Partitioning algorithm
performance evaluation

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10.1109/ISQED.2015.7085412

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Stefani, M. P., Webber, T., Fernandes, R., Cataldo, R., Poehls, L. B., & Marcon, C. (2015). Task partitioning optimization algorithm for energy saving and load balance on NoC-based MPSoCs. In Proceedings of the 16th International Symposium on Quality Electronic Design, ISQED 2015 (pp. 130-134). Article 7085412 (Proceedings - International Symposium on Quality Electronic Design, ISQED; Vol. 2015-April). IEEE Computer Society. https://doi.org/10.1109/ISQED.2015.7085412

@inproceedings{13d8350e08814daaa48078e024bd1578,

title = "Task partitioning optimization algorithm for energy saving and load balance on NoC-based MPSoCs",

abstract = "Multiprocessor System-on-Chip (MPSoC) based on Network-on-Chip (NoC) integrates a large amount of Processor Elements (PEs) to fulfill the performance requirements of several applications. These applications are composed of a set of intercommunicating tasks, which are dynamically mapped onto PEs of the target architecture. However, the efficient task-mapping requires some previous steps, among them partitioning, which organizes tasks considering their interaction before applying a mapping process. This paper introduces Partition Reduce (PR) - a task partitioning approach based on the MapReduce algorithm targeting homogeneous NoC based MPSoCs. We analyze the efficiency of PR for energy consumption (EC) minimization and load balance (LB). The results obtained from a set of experiments, with large number of tasks, demonstrate that PR is more effective on processing time and result quality when compared to the classic Simulated Annealing (SA). In addition, PR produces partitions with low energy consumption and rigorous load balance.",

keywords = "energy efficiency, homogeneous MPSoC, load balance, NoC, Partitioning algorithm, performance evaluation",

author = "Stefani, \{Marco P.\} and Thais Webber and Ramon Fernandes and Rodrigo Cataldo and Poehls, \{Let{\'i}cia B.\} and C{\'e}sar Marcon",

note = "Publisher Copyright: {\textcopyright} 2015 IEEE. Copyright: Copyright 2015 Elsevier B.V., All rights reserved.; 16th International Symposium on Quality Electronic Design, ISQED 2015 ; Conference date: 02-03-2015 Through 04-03-2015",

year = "2015",

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day = "13",

doi = "10.1109/ISQED.2015.7085412",

language = "English",

series = "Proceedings - International Symposium on Quality Electronic Design, ISQED",

publisher = "IEEE Computer Society",

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Stefani, MP, Webber, T, Fernandes, R, Cataldo, R, Poehls, LB & Marcon, C 2015, Task partitioning optimization algorithm for energy saving and load balance on NoC-based MPSoCs. in Proceedings of the 16th International Symposium on Quality Electronic Design, ISQED 2015., 7085412, Proceedings - International Symposium on Quality Electronic Design, ISQED, vol. 2015-April, IEEE Computer Society, pp. 130-134, 16th International Symposium on Quality Electronic Design, ISQED 2015, Santa Clara, United States, 2/03/15. https://doi.org/10.1109/ISQED.2015.7085412

Task partitioning optimization algorithm for energy saving and load balance on NoC-based MPSoCs. / Stefani, Marco P.; Webber, Thais; Fernandes, Ramon et al.
Proceedings of the 16th International Symposium on Quality Electronic Design, ISQED 2015. IEEE Computer Society, 2015. p. 130-134 7085412 (Proceedings - International Symposium on Quality Electronic Design, ISQED; Vol. 2015-April).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - Task partitioning optimization algorithm for energy saving and load balance on NoC-based MPSoCs

AU - Stefani, Marco P.

AU - Webber, Thais

AU - Fernandes, Ramon

AU - Cataldo, Rodrigo

AU - Poehls, Letícia B.

AU - Marcon, César

PY - 2015/4/13

Y1 - 2015/4/13

N2 - Multiprocessor System-on-Chip (MPSoC) based on Network-on-Chip (NoC) integrates a large amount of Processor Elements (PEs) to fulfill the performance requirements of several applications. These applications are composed of a set of intercommunicating tasks, which are dynamically mapped onto PEs of the target architecture. However, the efficient task-mapping requires some previous steps, among them partitioning, which organizes tasks considering their interaction before applying a mapping process. This paper introduces Partition Reduce (PR) - a task partitioning approach based on the MapReduce algorithm targeting homogeneous NoC based MPSoCs. We analyze the efficiency of PR for energy consumption (EC) minimization and load balance (LB). The results obtained from a set of experiments, with large number of tasks, demonstrate that PR is more effective on processing time and result quality when compared to the classic Simulated Annealing (SA). In addition, PR produces partitions with low energy consumption and rigorous load balance.

AB - Multiprocessor System-on-Chip (MPSoC) based on Network-on-Chip (NoC) integrates a large amount of Processor Elements (PEs) to fulfill the performance requirements of several applications. These applications are composed of a set of intercommunicating tasks, which are dynamically mapped onto PEs of the target architecture. However, the efficient task-mapping requires some previous steps, among them partitioning, which organizes tasks considering their interaction before applying a mapping process. This paper introduces Partition Reduce (PR) - a task partitioning approach based on the MapReduce algorithm targeting homogeneous NoC based MPSoCs. We analyze the efficiency of PR for energy consumption (EC) minimization and load balance (LB). The results obtained from a set of experiments, with large number of tasks, demonstrate that PR is more effective on processing time and result quality when compared to the classic Simulated Annealing (SA). In addition, PR produces partitions with low energy consumption and rigorous load balance.

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KW - load balance

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KW - performance evaluation

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BT - Proceedings of the 16th International Symposium on Quality Electronic Design, ISQED 2015

PB - IEEE Computer Society

T2 - 16th International Symposium on Quality Electronic Design, ISQED 2015

Y2 - 2 March 2015 through 4 March 2015

ER -

Stefani MP, Webber T, Fernandes R, Cataldo R, Poehls LB, Marcon C. Task partitioning optimization algorithm for energy saving and load balance on NoC-based MPSoCs. In Proceedings of the 16th International Symposium on Quality Electronic Design, ISQED 2015. IEEE Computer Society. 2015. p. 130-134. 7085412. (Proceedings - International Symposium on Quality Electronic Design, ISQED). doi: 10.1109/ISQED.2015.7085412

Task partitioning optimization algorithm for energy saving and load balance on NoC-based MPSoCs

Abstract

Publication series

Conference

UN SDGs

Keywords

Access to Document

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