Abstract
Asymmetric multicore processors (AMP) are necessary for extracting performance in an era of limited power budget and dark silicon. We have efficient symmetric schedulers, efficient asymmetric schedulers for single-threaded workloads, and efficient asymmetric schedulers for single program workloads. What we do not have is a scheduler that can handle all three factors affecting AMP scheduling: core affinity, thread criticality, and scheduling fairness.
To address this problem, this paper introduces the first general purpose asymmetry-aware scheduler targeting multi-threaded multi-programmed workloads. It estimates the performance of each thread on each type of core and it identifies communication patterns and bottleneck threads. With this information, the scheduler makes coordinated core assignment and thread selection decisions that still provide each application its fair share of the processor's time. We evaluated our approach on GEM5 through four distinct big.LITTLE configurations and multi-threaded multi-programmed workloads composed of PARSEC and SPLASH2 benchmarks. Compared against the Linux CFS scheduler and a state-of-the-art AMP-aware scheduler, we demonstrate performance gains of up to 25% and 5% to 15% on average depending on the hardware setup.
To address this problem, this paper introduces the first general purpose asymmetry-aware scheduler targeting multi-threaded multi-programmed workloads. It estimates the performance of each thread on each type of core and it identifies communication patterns and bottleneck threads. With this information, the scheduler makes coordinated core assignment and thread selection decisions that still provide each application its fair share of the processor's time. We evaluated our approach on GEM5 through four distinct big.LITTLE configurations and multi-threaded multi-programmed workloads composed of PARSEC and SPLASH2 benchmarks. Compared against the Linux CFS scheduler and a state-of-the-art AMP-aware scheduler, we demonstrate performance gains of up to 25% and 5% to 15% on average depending on the hardware setup.
Original language | English |
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Title of host publication | Proceedings of the 28th International Conference on Parallel Architectures and Compilation Techniques (PACT 2019) |
Publisher | IEEE Computer Society |
Pages | 486-487 |
Number of pages | 2 |
ISBN (Electronic) | 9781728136134 |
ISBN (Print) | 9781728136141 |
DOIs | |
Publication status | Published - 7 Nov 2019 |
Event | 28th International Conference on Parallel Architectures and Compilation Techniques - Seattle, United States Duration: 21 Sept 2019 → 25 Sept 2019 Conference number: 28 https://hpc.pnl.gov//pact19/ |
Publication series
Name | International Conference on Parallel Architectures and Compilation Techniques |
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ISSN (Print) | 1089-795X |
ISSN (Electronic) | 2641-7936 |
Conference
Conference | 28th International Conference on Parallel Architectures and Compilation Techniques |
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Abbreviated title | PACT19 |
Country/Territory | United States |
City | Seattle |
Period | 21/09/19 → 25/09/19 |
Internet address |