Lasio 3D NoC Vertical Links Serialization: Evaluation of Latency and Buffer Occupancy

Y Ghidini; M Moreira; L Brahm; T Webber; N Calazans; C Marcon

Lasio 3D NoC Vertical Links Serialization: Evaluation of Latency and Buffer Occupancy

Y Ghidini, M Moreira, L Brahm, T Webber, N Calazans, C Marcon

School of Computer Science

Research output: Book/Report › Book

Original language	English
Publication status	Published - 2013

Keywords

3D IC technology
Networks-on-Chip
TSV multiplexing
Through-Silicon Vias

Cite this

TY - BOOK

T1 - Lasio 3D NoC Vertical Links Serialization

T2 - Evaluation of Latency and Buffer Occupancy

AU - Ghidini, Y

AU - Moreira, M

AU - Brahm, L

AU - Webber, T

AU - Calazans, N

AU - Marcon, C

PY - 2013

Y1 - 2013

KW - 3D IC technology

KW - Networks-on-Chip

KW - TSV multiplexing

KW - Through-Silicon Vias

UR - https://www.webofscience.com/api/gateway?GWVersion=2&SrcApp=pure_st-andrews_wos_starter&SrcAuth=WosAPI&KeyUT=WOS:000704326600042&DestLinkType=FullRecord&DestApp=WOS

M3 - Book

BT - Lasio 3D NoC Vertical Links Serialization

ER -

Lasio 3D NoC Vertical Links Serialization: Evaluation of Latency and Buffer Occupancy

Keywords

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Cite this