@inproceedings{5d739c11f16144468e605ed06ac950b2,
title = "Efficient traffic balancing for NoC routing latency minimization",
abstract = "Modern technologies of integrated circuits allow billions of transistors arranged into a single chip, enabling to implement complex systems, which need a scalable and parallel communication architecture. Network-on-Chip (NoC) is a natural candidate to fulfill such communication requirements, providing high performance when the communication demands are balanced. This work proposes a new static balancing method that uses the application's traffic pattern for NoC latency reduction. This method allows the generation of a deterministic routing algorithm with simplistic implementation and low latency. Experimental results compare four balancing methods, showing the improvement of the proposed static balancing concerning the average NoC latency.",
keywords = "irregular topology, NoC, routing methods",
author = "Ferreira, {Joao M.} and Jarbas Silveira and Jardel Silveira and Rodrigo Cataldo and Thais Webber and Moraes, {Fernando G.} and Cesar Marcon",
note = "Publisher Copyright: {\textcopyright} 2016 IEEE. Copyright: Copyright 2017 Elsevier B.V., All rights reserved.; 2016 IEEE International Symposium on Circuits and Systems, ISCAS 2016 ; Conference date: 22-05-2016 Through 25-05-2016",
year = "2016",
month = jul,
day = "29",
doi = "10.1109/ISCAS.2016.7539125",
language = "English",
series = "Proceedings - IEEE International Symposium on Circuits and Systems",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "2599--2602",
booktitle = "ISCAS 2016 - IEEE International Symposium on Circuits and Systems",
address = "United States",
}