Buffer depth and traffic influence on 3D NoCs performance

Yan Ghidini*, Thais Webber, Edson Moreno, Fernando Grando, Rubem Fagundes, César Marcon

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)

Abstract

3D NoC-based architectures have emerged to reduce the network latency, the energy consumption and total area in comparison to 2D NoC topologies. However, they are characterized by various trade-offs with regard to the three dimensional structure and its performance specifications. In this paper, we present a 3D NoC mesh architecture called Lasio, whose latency and the throughput achieved, for both network and application, are evaluated considering two types of traffic patterns, varied buffer depth and a range of packet sizes. Cycle-accurate simulations demonstrated that there is a high impact of buffer depth and packet size on the NoC latency and on the application latency. Applying an appropriate buffer depth, for several sizes of packets, the application latency is reduced and throughput is increased.

Original languageEnglish
Title of host publicationProceedings of the 2012 23rd IEEE International Symposium on Rapid System Prototyping
Subtitle of host publicationShortening the Path from Specification to Prototype, RSP 2012
Pages9-15
Number of pages7
DOIs
Publication statusPublished - 2012
Event23rd IEEE International Symposium on Rapid System Prototyping, RSP 2012 - Tampere, Finland
Duration: 11 Oct 201212 Oct 2012

Publication series

NameProceedings - IEEE International Symposium on Rapid System Prototyping, RSP
ISSN (Print)2150-5500
ISSN (Electronic)2150-5519

Conference

Conference23rd IEEE International Symposium on Rapid System Prototyping, RSP 2012
Country/TerritoryFinland
CityTampere
Period11/10/1212/10/12

Keywords

  • 3D NoC
  • Buffer depth
  • Latency
  • Throughput

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