Abstract
Processor design tools integrate in their workflows generators for instruction set simulators (ISS) from architecture descriptions. However, it is difficult to validate the correctness of these simu-lators. ISA coverage analysis is insufficient to isolate modelling faults, which might only be exposed in corner cases. We present a novel ISA branch coverage analysis, which considers every possible execution path within an instruction and, on demand, generates new test cases to cover the missing paths. We have applied this analysis to industry standard EEMBC and SPEC CPU2006 benchmarks and show that for an ARM V5T model neither of these benchmark suites provides a sufficient ISA coverage to exercise every path through each instruction of the whole instruction set.
| Original language | English |
|---|---|
| Title of host publication | CASES '14: Proceedings of the 2014 International Conference on Compilers, Architecture and Synthesis for Embedded Systems |
| Place of Publication | New York, NY, United States |
| Publisher | ACM |
| Number of pages | 10 |
| ISBN (Electronic) | 978-1-4503-3050-3 |
| DOIs | |
| Publication status | Published - 1 Oct 2014 |
Keywords
- fault tolerant computing
- instruction sets
- program diagnostics
- program testing
- ARM V5T model
- EEMBC benchmark
- ISA branch coverage analysis
- ISS
- SPEC CPU2006 benchmark
- instruction execution path
- modelling fault isolation
- processor design tools
- retargetable instruction set simulators
- test case generation
- Benchmark testing
- Context
- Generators
- Registers
- Semantics
- Vectors