I am a Professor in Computer Science at the University of St Andrews, and have been here at St Andrews since 2013. Before this, I did postdoctoral work at the University of Cambridge, and obtained my PhD from Carnegie Mellon University. I am a Honorary Fellow at the School of Informatics of the University of Edinburgh, a Fellow of the British Computer Society (BCS), and a Senior Member of the Association of Computing Machinery (ACM).

My research interests are in concurrent and low-level software, and the software-hardware interface (others call this Architecture, or ISA-level). I have done work on memory consistency models, shared memory, dependent types, certified code, parallel cost models, and parallel code refactoring. My work has contributed to the understanding of the ARM, IBM POWER, x86, RISC-V architectures, the C, C++ and Java programming languages. I have served as an invited expert for the RISC-V architecture definition effort.

I am a REF 2029 panellist for Computer Science and Informatics. I have published and reviewed extensively for leading journals and conferences (PLDI, POPL, TOPLAS, ICFP), and reviewed/been on panels for the EPSRC/ERC/ANR(France).

My research interests are in specifying, validating, and verifying concurrent software and hardware. I particularly enjoy working at the hardware-software interface (low-level software/architecture-level hardware). Here I have worked extensively on the problem of memory consistency models, for architectures such as ARM, IBM POWER, RISC-V, and for low-level programming languages such as C/C++. I have pushed both down and up the stack, for example working on verification of cache protocols, of high-level parallel algorithmic skeletons, and on refactoring.

This academic year (2025-26) I am teaching:

• CS3050: Logic and Reasoning
• CS5030: Software Engineering Principles

In the past, I have taught modules at different levels, including:

• CS3052: Computational Complexity
• CS4204: Concurrency and Multi-Core Architectures
• IS5102: Database Management Systems
• CS2006: Advanced Programming Projects

I also supervise project students at various levels in the school.

Outside St Andrews: I have delivered short courses and tutorials at a variety of venues, most recently An Introduction to Reasoning with Weak Memory at the Scottish Programming Languages and Verification Summer School 2022 (SPLV'22).

Shared memory concurrency; parallelism; programming languages; verification; compilers; static analysis; hardware architecture design; memory consistency models