• KY16 9SS

    United Kingdom

Accepting Postgraduate Research Students

PhD projects

Shared memory concurrency; verification; parallelism; programming languages; compilers; static analysis; hardware architecture design; memory consistency models

Personal profile

Biography

I am a Professor in Computer Science at the University of St Andrews, and have been here at St Andrews since 2013. Before this, I did postdoctoral work at the University of Cambridge, and obtained my PhD from Carnegie Mellon University. I am a Honorary Fellow at the School of Informatics of the University of Edinburgh, a Fellow of the British Computer Society (BCS), and a Senior Member of the Association of Computing Machinery (ACM).

My research interests are in concurrent and low-level software, and the software-hardware interface (others call this Architecture, or ISA-level). I have done work on memory consistency models, shared memory, dependent types, certified code, parallel cost models, and parallel code refactoring. My work has contributed to the understanding of the ARM, IBM POWER, x86, RISC-V architectures, the C, C++ and Java programming languages. I have served as an invited expert for the RISC-V architecture definition effort, published and reviewed extensively for leading journals and conferences (PLDI, POPL, TOPLAS, ICFP), and reviewed/been on panels for the EPSRC/ERC/ANR(France).

Research overview

My research interests are in specifying, validating, and verifying concurrent software and hardware. I particularly enjoy working at the hardware-software interface (low-level software/architecture-level hardware). Here I have worked extensively on the problem of memory consistency models, for architectures such as ARM, IBM POWER, RISC-V, and for low-level programming languages such as C/C++. I have pushed both down and up the stack, for example working on verification of cache protocols, of high-level parallel algorithmic skeletons, and on refactoring.

Teaching activity

This academic year (2023-24) I am teaching:

  • CS3050: Logic and Reasoning
  • CS4204: Concurrency and Multi-Core Architectures
  • CS5031: Software Engineering Practice

In the past, I have taught modules at different levels, including:

  • CS3052: Computational Complexity
  • IS5102: Database Management Systems
  • CS2006: Advanced Programming Projects

I also supervise project students at various levels in the school.

Outside St Andrews: I have delivered short courses and tutorials at a variety of venues, most recently An Introduction to Reasoning with Weak Memory at the Scottish Programming Languages and Verification Summer School 2022 (SPLV'22).

Profile Keywords

Shared memory concurrency; parallelism; programming languages; verification; compilers; static analysis; hardware architecture design; memory consistency models

Education/Academic qualification

Doctor of Philosophy, Computer Science, Carnegie Mellon University

5 Aug 200114 May 2009

Award Date: 14 May 2009

Bachelor of Technology (not to be confused with BTEC), Computer Science and Engineering, Indian Institute of Technology

1 Sept 19975 Jul 2001

Award Date: 5 Jul 2001

External positions

Honorary Fellow, University of Edinburgh

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  • Compound memory models

    Goens, A., Chakraborty, S., Sarkar, S., Agarwal, S., Oswald, N. & Nagarajan, V., 6 Jun 2023, In: Proceedings of the ACM on Programming Languages. 7, PLDI, 24 p., 153.

    Research output: Contribution to journalArticlepeer-review

    Open Access
    File
    12 Downloads (Pure)
  • Fast and correct load-link/store-conditional instruction handling in DBT systems

    Kristien, M., Spink, T., Campbell, B., Sarkar, S., Stark, I., Franke, B., Böhm, I. & Topham, N., 2 Oct 2020, CASES '20: Proceedings of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems. IEEE Computer Society, Vol. Early Access. 11 p. (IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Open Access
    File
    5 Downloads (Pure)
  • Simplifying ARM concurrency: multicopy-atomic axiomatic and operational models for ARMv8

    Pulte, C., Flur, S., Deacon, W., French, J., Sarkar, S. & Sewell, P., Jan 2018, Proceedings of the ACM on Programming Languages (POPL '18). New York: ACM, p. 1-29 29 p. 19. (Proceedings of the ACM on Programming Languages; vol. 2, no. POPL).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Open Access
    File
    17 Downloads (Pure)
  • Verification of a lazy cache coherence protocol against a weak memory model

    Banks, C., Elver, M., Hoffmann, R., Sarkar, S., Jackson, P. & Nagarajan, V., 2 Oct 2017, Proceedings of the 17th Conference on Formal Methods in Computer-Aided Design (FMCAD 2017). Stewart, D. & Weissenbacher, G. (eds.). FMCAD Inc, p. 60-67

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Open Access
    File
    3 Citations (Scopus)
    1 Downloads (Pure)
  • Mixed-size concurrency: ARM, POWER, C/C++11, and SC

    Flur, S., Sarkar, S., Pulte, C., Nienhuis, K., Maranget, L., Gray, K., Sezgin, A., Batty, M. & Sewell, P., 1 Jan 2017, Proceedings of the 44th annual ACM-SIGPLAN Symposium on Principles of programming languages (POPL 2017). Fluet, M. (ed.). New York: ACM, p. 429-442 14 p. (ACM SIGPLAN Notices; vol. 52, no. 1).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Open Access
    File
    8 Citations (Scopus)
    15 Downloads (Pure)